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[VHDL-FPGA-Verilog] FPGAdigitaltimer

Description: 本设计要实现一个具有预置数的数字钟的设计,具体要求如下: 1. 正确显示年、月、日 2. 正确显示时、分、秒 3. 具有校时,整点报时和秒表功能 4. 进行系统模拟仿真和下载编程实验,验证系统的正确性 -designed to achieve this with a number of preset clock design, and specific requirements are as follows : 1. Display correctly, , 2. display correctly when, minutes and 3 seconds. with school, the whole point timekeeping and stopwatch functions 4. for system simulation and download programming an experiment to test the correctness of system
Platform: | Size: 502784 | Author: wangpeng | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[VHDL-FPGA-Verilog] 8253

Description: With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
Platform: | Size: 7168 | Author: 靖书磊 | Hits:

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

Description: 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three experiments _SOPC_LED programmer _Flash the basis of four experiments of five experiments _ timer six experimental basis _ keys, as well as experimental experimental PIO interrupt I _ 7 card use, these laboratories used the SOPC BUILDER with NOIS ii, the use of Verilog to prepare, there are no experimental test panels and plates can be used to learn. The second also includes: FPGA development board of the links between memory, multi-processor documents, USB_UART such as documents, useful documents, you will not regret it a sure!
Platform: | Size: 6065152 | Author: yuezhiying_007 | Hits:

[VHDL-FPGA-Verilog] gh_timer_8254

Description: VHDL Source code for 8254 timer/counter
Platform: | Size: 106496 | Author: Alireza | Hits:

[SCM] mcu-fpga

Description: 用于MSP430的定时器功能的程序段,使大家可以充分了解和熟练单片机定时器的使用。-MSP430 timer function for the program segment and to enable them to fully understanding and proficiency in the use of single-chip timer. 搜索
Platform: | Size: 3072 | Author: 王雄科 | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[Embeded-SCM Develop] DigitalClock

Description: 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results.
Platform: | Size: 63488 | Author: sunnan | Hits:

[VHDL-FPGA-Verilog] pwm_timer

Description: PWM和Timer的FPGA实现，文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.
Platform: | Size: 271360 | Author: kele | Hits:

[VHDL-FPGA-Verilog] RS232_FIR

Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
Platform: | Size: 202752 | Author: jay | Hits:

[VHDL-FPGA-Verilog] basketball24

Description: 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
Platform: | Size: 1024 | Author: cynthia | Hits:

[VHDL-FPGA-Verilog] nios-II

Description: NiosII范例，包括了DMA控制，串口通信，定时器中断，以及NIOS的部分范例，对于FPGA内核的开发很有帮助。-NiosII example, including the DMA control, serial communication, timer interrupt, as well as some examples of NIOS, development will be helpful for the FPGA core.
Platform: | Size: 204800 | Author: 张奎 | Hits:

[VHDL-FPGA-Verilog] 24

Description: 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
Platform: | Size: 1024 | Author: 单俍 | Hits:

[VHDL-FPGA-Verilog] led

Description: FPGA做的led流水灯，quartus搭的nios，计时器每隔一秒led点亮一次，四个流水灯循环显示，适合新手学习-FPGA do led light water, quartus ride nios, timer once every second led lights, four light water cycle, for beginners to learn
Platform: | Size: 14083072 | Author: 勇磊 | Hits:

[Other] FPGA-timer

Description: fpga时序收敛的设计培训教程，很适合大家学习，适合入门-fpga design training tutorial timing closure, it is suitable for everyone to learn, for entry
Platform: | Size: 1999872 | Author: 吕攀攀 | Hits:

[VHDL-FPGA-Verilog] Gameone

Description: 此秒表有两个按键（reset， start）按下reset键后，秒表清零，按下start键后，开始计时， 再次按下start键后， 停止计时， 用FPGA开发板上的两个七段数码管显示时间（以秒为单位），计时由0 到 59 循环。 高级要求（可选）：实现基本要求的前提下，增加一个按键（select），用于轮流切换两个七段数码管分别显示百分之一秒，秒，分钟。 规格说明： 1.通过按下reset键（异步复位），将秒表清零，准备计时，等检测到start键按下并松开后，开始计时 。如果再次检测到start键按下并松开后，停止计时。通过不断检测start键，来确定秒表是否开始计时 2.在秒表计时时，七段数码管能够循环的由00…59,00…59…。 3.开始默认两个七段数码管显示秒， 在检测到select键按下并松开后，数码管切换到显示分钟，再次检测到select键按下并松开后，数码管切换到显示百分之一秒，当再次检测到select键按下并松开后，数码管切换到重新显示秒。 4.在秒表停止时，数码管依然能够正常切换显示百分之一秒，秒，分钟。-This stopwatch has two buttons (reset, start) press the reset button after the stopwatch is cleared, press the start button to start the timer, press the start button again to stop the clock, seven with two FPGA development board digital display time (in seconds), time the 0-59 cycle. Advanced requirements (optional): to achieve the basic requirements under the premise of adding a button (select), for alternately switching between two seven-segment LED display are hundredths of a second, seconds, minutes. Specifications: 1. Press the reset button (asynchronous reset), the stopwatch is cleared in preparation for timing, and other testing to start Press and release the start timing. If the detected start button press and release again to stop the clock. By constantly testing the start key to determine whether to start the stopwatch timer 2. When the stopwatch, the seven segments can be recycled by ... 59 ... 00 ... 59.00. 3. Start the default two seven-segment LED display seconds after
Platform: | Size: 2789376 | Author: XiaoLiuMang | Hits:

[VHDL-FPGA-Verilog] pluse_count

Description: 以利用FPGA系统时钟分频对定时器进行配置和定时操作。-To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly
Platform: | Size: 1024 | Author: KO | Hits:

[VHDL-FPGA-Verilog] uart

Description: （1）利用串口实现发送功能，即利用计算机上的串口调试小助手定时显示“HELLO WORLD”字样；（2）利用串口实现接收功能，并将接收到的字符再通过串口发送到计算机上的串口调试小助手上显示，例如：利用串口小助手的手动发送功能向串口发送“Good Good Study，day day up”，然后利用FPGA实现转发，将字符从串口发送回串口调试小助手显示。-(2) the use of serial port to achieve the receiving function, and the received characters through the serial port to send to the serial port on the computer (1) the use of serial port to achieve the sending function, that is, the use of computer serial debugging small assistant timer display HELLO WORLD words Debugging small assistant display, for example: the use of serial communication assistant to send the function to the serial port to send Good Good Study, day day up , and then use the FPGA to achieve forwarding, the characters sent back the serial port debugging small assistant display.
Platform: | Size: 1146880 | Author: 王宁 | Hits:

[SCM] timer

Description: ARM m4 FPGA开发模块，用于timer模块的开发(ARM M4 FPGA development module, used for the development of timer module)
Platform: | Size: 10240 | Author: Clancey | Hits:

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